All-Digital PLL(ADPLL) is a key component in ultra-low power wireless transceivers. The ADPLL is required for high-integrated design to achieve low design cost and easier implementation. This project focuses on designing the low power and low noise ADPLL using ring oscillator.
All-digital PLLs (ADPLLs) have been widely used for frequency synthesizer in modern wireless transceivers. ADPLLs can achieve low power dissipation and high-level integration with diverse testability. In ADPLLs, DCO and TDC/DTC are critical sub-blocks for overall ADPLL performance.
Ring oscillator is traditionally considered to implement DCO. While the ring DCO has high integrity and wide frequency coverage, it is difficult to design in a power efficient scheme with low phase noise requirement.
TDC/DTC has also a decisive role to detect phase difference in ADPLLs. Its non-ideal time-to-digital conversion degrades in-band phase noise and spur characteristics on ADPLLs' output.
In this project, three main goals will be implemented in advanced CMOS technology:
- Low power and noise ring-oscillator DCO design;
- High performance TDC/DTC design;
- Overall ADPLL design and its verification
- Literature studies on state-of-the-art frequency synthesizers;
- Understanding both analog and digital design methodologies;
- Architecture study and proposal;
- Circuit implementation;
- Layout and post-layout simulation;
- Tape-out and measurement.
- Good analytical skills;
- Knowledges of designing CMOS circuits;
- Motivated student eager to work independently and expand knowledge in the field;
- Good written and verbal English skills.
For all inquiries, please contact:
Ms Najat Loiazizi, HR specialist.
Telephone number: +31 (0)40 40 20 675