Exploration of advanced power gating techniques
At imec, Ultra low power DSP
For advanced process technology nodes leakage power increasingly contributes to integrated circuit (IC) total power consumption. By using power gating specific parts of an IC can be selectively cut-off from the power supply when their functionality is not required at a certain moment in time, hence reducing the overall leakage power consumption. However, power gating induces overheads in terms of time, energy and area that have to be considered in the design process. In this thesis the use advanced power gating techniques will be explored and their impact on the system will be evaluated.
Tasks
-
Literature research on advanced power gating techniques
-
Concept for advanced power gating in an ultra low power DSP architecture for wireless sensor nodes
-
Implementation of proposed concept
-
Evaluation of results (power simulations) against reference architecture
Requirements
We are looking for a motivated MSc-student with the following background:
-
in Electrical Engineering or Computer Sciences;
-
interest in digital circuit design;
-
experience VHDL / Verilog and EDA-related tools (Cadence, Synopsys) is considered a plus;
-
experience in circuit simulation using a spice simulator (e.g. spectre, pSpice) is considered a plus;
-
good verbal and written communication skills in English.
For all inquiries, please contact:
Ms Sandra Maas, Management Assistant Human Resources.
Telephone number: +31 (0)40 40 20 500.
Application form